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1 june 1, 1999; data device corp. description the pwr-82521 is a high perfor- mance current regulating torque loop controller. it is designed to accurately regulate the current in the windings of 3-phase brushless dc and brush dc motors. the pwr-82521 is a completely self- contained motor controller that con- verts the analog input command sig- nal into motor current and uses the signals from hall-effect sensors in the motor to commutate the current in the motor windings. the motor current is internally sensed and processed into an analog signal. this signal is summed together with the command signal to produce an error signal that controls the pulse width modulation (pwm) duty cycle of the output, thus controlling the motor current. the pwr-82521 can be tuned by using an external proportional-integral (pi) reg- ulator network in conjunction with the internal error amplifier. applications packaged in a small dip-style hybrid, the pwr-82521 are ideal for applica- tions with limited printed circuit board area. the pwr-82521 is ideal for applica- tion requiring current regulation and/or holding torque at zero input com- mand. system applications include flight surface control on aircraft for horizontal stabilizers and flaps, missile fin control, fuel and hydraulic pumps, radar and countermeasures systems. 3-phase dc motor torque controller features ? 200v rating ? 10 amp continuous output current ? complementary four-quadrant operation ? 3% linearity accuracy ? 5% current regulating accuracy ? user-programmable compensation ? 10 khz - 50 khz pwm frequency ? operates as current or voltage controller ? self-contained 3-phase motor controller ? built-in current limit figure 1. pwr-82521 block diagram pwr-82521 drive a drive b drive current c phase a 14,15,16 phase a phase b 7,8,9 phase b phase c 1,2,3 phase c vbus+ 4,5,6 pwm logic circuitry commutation logic ha hb hc 5.0v 10k 10k 10k vbusC 11,12,13 rsense pwm in v dd + + 10k 5.0v error amplifier 100 - - + - + + amp command buffer 100 10k 10k 10k 10k hall a command out command in + command in - +15v +15v hall supply output supply gnd enable +15v supply ground -15v supply pwm out pwm gnd 39 command gnd 37 36 38 35 34 33 32 31 30 29 28 27 26 21 19 17 40 41 20 case gnd case error amp out error amp in current monitor out 100 22 sync in v ee is+ 10 hall b hall c hall 90.9
june 1, 2000; data device corp. note: 1) i oc is average current as measured in motor winding 2) guaranteed by design, not tested. 3) the maximum output conductor resistance and on-resistance of fets at +85c are: f a u = 0.20 w, f a l = 0.16 w, f b u = 0.08 w, f b l = 0.08 w, f c u = 0.08 w, f c l = 0.20 w table 1. absolute maximum ratings (tc = +25c unless otherwise specified) parameter symbol value units bus voltage vbus+ 200 vdc continuous output current +15v supply i oc v dd 10 +17.5 a vdc peak output current -15v supply i peak v ee 18 -17.5 a vdc command input + command input+ 15 vdc sync input command input - sync command input- 15.0 15 vdc vdc logic inputs enable ha, hb, hc 7.0 vdc table 2. pwr-82521 specifications (unless otherwise specified, vbus = 28 vdc, v dd = +15v, v ee = -15v, t c = 25c) sync (note 2) voltage pulse width sync range as % of free-run frequency see figure 7 7.5 130 0 +20 parameters symbol test conditions value v ns % units min typ max output output current continuous output current pulsed current limit current offset output on-resistance output on-resistance output conductor resistance load inductance i oc (note 1) i op i cl i offset r on (note 2, 3) r on (note 2, 3) r c l min v df = 0v +25c +85c +85c 15.3 -0.3 100 18.0 - note 3 10 18 19.8 +0.3 0.100 0.140 a a a a w w w m h command in+/- differential input v dif -10 +10 vdc command out internal voltage clamp v clmp -11.5 +11.5 vdc vbus- to pwm gnd voltage differential current command transconductance ratio non-linearity v gnddif g see figure 9 0.95 -3.0 1.0 0.250 1.05 +3.0 vdc a/v % current monitor amp current monitor gain current monitor offset output current output resistance r out v df = 0v 0.97 -0.1 -10 1.0 0 1.03 0.1 10 100 v/a vdc ma w vbus+ supply nominal operating voltage v nom +18 +28 +140 vdc +15 vdc voltage current v s + i + +14.25 +15.0 100 +15.75 150 vdc ma -15 vdc voltage current v s - i - -15.75 -15.0 80 -14.25 150 vdc ma
3 june 1, 1999; data device corp. introduction the pwr-82521 is high performance current control (torque loop) hybrid which use complementary four quadrant switching topology (see basic operation) to provide linearity through zero current. the high pulse width modulation (pwm) switching frequency makes it suitable for even low inductance motors. the pwr-82521 hybrid can accept single-ended or differential mode command signals. the current gain can be easily programmed to match the end user system requirements. with the compen- sation network externally wired, the hybrid can provide optimum control of a wide range of loads. the pwr-82521 uses unique current sense technology and a non-inductive hybrid sense resistor which yields a highly linear current output over the wide military temperature range (see figure 9). the output current non-linearity is better than 3% over the operating temperature range and the total error due to all the factors such as offset, initial component accuracies etc. is maintained well below 5% of the rated output current. the hall sensor interface for current commutation has built-in decoder logic that separates illegal codes and ensures that there is no cross conduction. the hybrid also has a +15v supply out- put for powering the hall sensors. the hall sensor inputs are internally pulled up to +5v and they can be driven from open-col- lector outputs. the pwm frequency can be programmed externally by adding a capacitor from pwm out to pwm gnd. in addition, multiple pwr-82521s can be synchronized by using one device as a master and connecting its pwm out pin to the pwm in of all the other slave devices in a system or by applying a sync pulse to pin 22. table 2. pwr-82521 specifications (continued) (unless otherwise specified, vbus = 28 vdc, v dd = +15v, v ee = -15v, t c = 25c) parameters symbol test conditions value units min typ max pwm in +peak -peak frequency non -linearity duty cycle v p + v p - f lin d cycle 9.8 -10.2 10 -2 49 10.0 -10.0 50 10.2 -9.8 60 +2 51 v v khz % % pwm out free run frequency 45 50 55 khz hall power supply max current draw i mdrw 50 ma hall signals logic 1 logic 0 ha, hb, hc 3.5 0.7 vdc vdc enable input enabled disabled enable 3.5 0.7 vdc isolation case to pin 500 vdc hipot 10 m w thermal thermal resistance junction - case case - air junction temperature case operating temperature case storage temperature propagation delay switching charac teristics upper drive turn-on rise time turn-off fall time lower drive turn-on rise time turn-off fall time diode forward voltage drop q j-c q c-a t j t c t cs td (on) td (off) tr tf tr tf v f ip = 4a from 0.7v on enable to 10% of vout from 3.5v on enable to 90% of vout i p =4 a i d = 1a -55 -65 40 20 6 10 +175 +125 +150 tbd tbd tbd tbd 1.9 c/w c/w c c c s s ns ns ns ns v weight 1.7(48) oz(gr)
4 june 1, 2000; data device corp. v bus phase a upper phase a lower phase b upper phase b lower rsense phase a phase b phase c - + off off on on i figure 2a. complementary 4-quandrant drive first half of pwm cycle v bus phase a upper phase a lower phase b upper phase b lower rsense phase a phase b phase c + _ on on off off i figure 2b. complementary 4-quandrant drive second half of pwm cycle the enable input signal provides quick start and shutdown of the output power switches. in addition, built-in power sequence fault protection turns off the output in case of low power supply voltages. the hybrid features dual current limiting functions. the input command amplifier output is limited to 10.8v thus limiting the current under normal operation. in addition, there is a built in over current limit which trips at 18 amps, protecting the hybrid as well as the load. basic operation the pw-82521 utilizes a complimentary four-quadrant drive technique to control current in the load. the complimentary drive has the following advantages over the standard drive: 1. maximum holding torque and position accuracy 2. linear current control through zero 3. no deadband at zero the complementary drive design uses a 50% pwm duty cycle for a zero command signal. for a zero input command, a pair of mosfets are turned on in the drive, phase a upper & phase b lower as shown in figure 2a, to supply current into the load for the first half of the pwm cycle. this is the same mode of oper- ation for the standard 4-quadrant drive as shown in figure 3a/b. during the second half of the pwm cycle, a second pair of transistors are turned on, phase a lower & phase b upper as shown in figure 2b, for the flyback current and to provide load current in the opposite direction. this is normally the dead time for standard 4-quadrant drive as shown in figure 3b. the result is current flowing in both direc- tions in the motor for each pwm cycle. the advantage this has over standard 4-quadrant drive is that at 50% duty cycle, which corresponds to zero average current in the motor, holding torque is provided. the motor current at 50% duty cycle is simply the magnetizing current of the motor winding. using the complimentary 4-quadrant technique allows the motor direction to be defined by the duty cycle. relative to a given switch pair, i.e. phase a upper and phase b lower, a duty cycle greater than 50% will result in a clockwise rotation whereas a duty cycle less than 50% will result in a counter clockwise rota- tion. therefore, with the use of average current mode control, direction can be controlled without the use of a direction bit and the current can be controlled through zero in a very precise and linear fashion. the pw-82521 contains all the circuitry required to close an average current mode control loop around a complimentary 4- quadrant drive. the pwr-82521 use of average current mode control simplifies the control loop by eliminating the need for slope compensation and eliminating the pole created by the motor inductance. these two effects are normally associated with 50% duty cycle limitations when implementing standard peak current mode control.
5 june 1, 1999; data device corp. v bus phase a upper phase a lower phase b upper phase b lower rsense phase a phase b phase c - + off off on on i v bus phase a upper phase a lower phase b upper phase b lower rsense phase a phase b phase c + _ off off off off i flyback figure 3a. standard 4 quandrant drive first half of pwm cycle figure 3b. standard 4 quandrant drive second half of pwm cycle functional and pin descriptions: command in+, command in- (pins 30 & 31) the command amplifier has a differential input that operates from a 10 v analog current comand. the differential input volt- age may vary between 10 vdc, maximum, corresponding to maximum voltage or current for the output. either input (com- mand in + or command in-) may be referenced to the com- mand ground (pin 29) and the other input varied from 10 vdc to obtain full output. the command out signal is internally lim- ited to approximately 11.5 vdc; that is, inputs above or below 11.5 vdc will be clamped to 11.5 vdc. the input impedance of the command amplifier is 10k ohms. the pwr-82521 can be used either as a current or voltage mode controller. when the pwr-82521 is used as a torque amplifier (current mode) as shown in figure 13, the transfer function of the command amplifier is 1.0 a/v. the input com- mand signal is processed through the command buffer. the out- put of the buffer (command out) is summed with the current monitor output into the error amplifier. when external compen- sation is used on the error amp, as shown in figure 6a, the response time can be adjusted to meet the application. when used in the voltage mode the voltage command uses the same differential input terminals to control the voltage applied to the motor (see figure 12). the error amp directly varies the pwm duty cycle of the voltage applied to the motor phase. the transfer function in the voltage mode is 4.7% /v 5% variation of the pwm duty cycle vs. input command. the duty cycle range of the output voltage is limited to approximately 5-95% in both cur- rent and voltage modes. transconductance ratio and offset when the pwr-82521 is used in the current mode, the com- mand inputs (command in+ and command in-) are designed such that 10 vdc on either input, with the other input connect- ed to ground, will result in 10 dc average amperes of current into the load. the dc current transfer ratio accuracy is 5% of the rated output current. the initial output dc current offset with both command in+ and command in- tied to the ground will be less than 100 ma when measured using a load of 0.5 mh and 1.0 ohms at room ambient with standard current loop compen- sation (see figure 6a). the winding phase current error shall be within the cumulative limits of the transconductance ratio error and the offset error. hall a,b,c signals (pins 37, 38 and 39) these are logic signals from the motor rotor position sensors (ha, hb, hc). they use a phasing convention referred to as 120 degree spacing; that is, the output of ha is in phase with motor back emf voltage vab, hb is in phase vbc, and hc is in phase with vca. logic 1 (or high) is defined by an input greater than 3.5 vdc or an open circuit to the controller; logic 0 (or low) is defined as any hall voltage input less than 0.7 vdc. internal to the pwr-82520 are 5k pull-up resistors tied to +5 vdc on each hall input. the pwr-82521 will operate with hall phasing of 60 or 120 electrical spacing. if 60 commutation is used, then the output of
6 june 1, 2000; data device corp. external pi regulator 10.0 k r1 4700 pf c1 1 meg error amp input command out current monitor out r2a 10.0 k r2b 10.0 k - + o error amp out 32 35 33 34 470 pf r7 figure 6a. standard pi current loop 200 a, db 100 0 -100 180 q , degree 90 10hz 100hz 1.0khz 10khz 100khz 1.0mhz 10mhz 100mhz frequency 0 figure 6b. pi regulator frequency response hall-effect sensor phasing vs. motor back emf for cw rotation (120 commutations) 300 0 60 120 180 240 300 360 /0 60 v ab v bc v ca back emf of motor rotating cw cw ha hb hc hc in phase with v ab in phase with v bc in phase with v ca in phase with v ac (60?) figure 4. hall phasing s hc ha 120 n hb 120 n hc 120 remote position sensor (hall) spacing for 120 degree commutation 60 60 remote position sensor (hall) spacing for 60 degree commutation s ha hb hc figure 5. hall sensor spacing hc must be inverted as shown in figures 4 and 5. in figure 4, the hall sensor outputs are shown with the corresponding volt- age they are in phase with. hall input signal conditioning: when the motor is located more than two feet away from the pwr-82520 controller the hall inputs require filtering from noise. it is recommended to use a 1k w resistor in series with the hall signal and a 2000 pf capac- itor from the hall input pin to the hall supply ground pin as shown in figure 12 and 13. compensation the pi regulator in the pwr-82521 can be tuned to a specific load for optimum performance. figure 6a shows the standard current loop configuration and tuning components, and figure 6b shows the frequency response for the pi regulator. by adjust- ing r1, r2 and c1, the amplififer can be tuned. the value of r1, c1 will vary, depending on the loop bandwidth requirement.
enable ( pin 36 ) this is a logic input to the controller that enables or disables the controller. in the disabled state, no voltage shall be applied to the motor phases. the disabled state occurs when the enable input is greater than 3.5 vdc or is left open; to enable the controller, this input must be pulled to less than 0.7 vdc. the enable input has a 10k pull-up resistor tied to +5 vdc. vbus+ (pins 4, 5 and 6) the vbus+ supply is the power source for the motor phases and is nominally +28 vdc. the normal operating voltage may actu- ally vary from +18 to +140 vdc with respect to vbus-. the power stage mosfets in the hybrid have an absolute maximum vbus+ supply voltage rating of 200v. the user must supply suf- ficient external capacitance or circuitry to prevent the bus supply from exceeding +200 vdc at the hybrid power terminals under any conditions. the vbus should be applied at least 50 ms after 15 vdc to allow the internal analog circuitry to stabilize. if this is not possi- ble, the hybrid must be powered up in the disabled mode. vbus- (pins 11, 12, and 13) this is the high current ground return for vbus+. this point must be externally connected to ground for proper operation of the current loop. the voltage difference between vbus- and the ground connections must be less than 0.250 vdc including transients. grounds supply gnd (pin 27): this is the return line for the 15 vdc supplies. the phase current sensing technique of the pwr-82521 requires that vbus- and supply ground be con- nected together externally (see vbus- supply). pwm gnd (pin 21): this is used for the return side of the exter- nal pwm capacitor (cext) when switching frequencies below 50 khz are required. command gnd (pin 29): this is used when the command buffer is used single-ended and the command in- or com- mand in+ are tied to command gnd. hall gnd (pin 41): this is used for the return of the +15v hall supply and should be tied to supply ground. 15 vdc (+15v supply, pin 28 / -15v supply, pin 26) these inputs are used to power the small signal analog and dig- ital circuitry of the hybrid. an internal +5 vdc supply is derived from the +15 vdc source. these inputs should not vary more than 5%, maximum. the absolute maximum voltage ratings of these inputs are 17.5 vdc. reversal of the power supplies will result in destruction of the hybrid. sync in (pin 22) the sync pulse, as shwown in figure 7, can be used to syn- chronize the switching frequency up to 20% faster than the free running frequency of all th slave devices. 7 june 1, 1999; data device corp. pwm frequency the pwm frequency from the pwm out pin will free-run at a frequency of 50 khz 10 khz. the user can adjust this frequen- cy down to 10 khz through the addition of an external capacitor. the pwm triangle wave generated internally is brought out to the pwm out pin. this output, or an external triangle waveform generated by the user, may be connected to pwm in on the hybrid. pwm out (pin 20) this is the output of the internally generated pwm triangle wave form. it is normally connected to pwm in. the frequency of this output may be lowered by connecting an npo capacitor (cext) between pwm out and pwm gnd. the typical pwm frequen- cy is determined by the following formula: case (pin 17) this pin is internally connected to the hybrid case. in some appli- cations the user may want to tie pin 17 to ground for emi con- siderations. phases a, b, c (pin a 14-16, b 7-9, c 1-3) these are the power drive outputs to the motor and switch between vbus+ input and vbus- input or become high imped- ance - see table 3. +15 vdc hall supply output (pin 40) this output provides power to the hall sensors in the motor. maximum current drawn from this supply by the user must not exceed 50 ma. warning: never apply power to the hybrid without connecting either pwm out or an external triangular wave to pwm in! failure to do so may result in one or more outputs latching on. +7.5v -7.5v sync period 130ns figure 7. sync input signal 16.5e-6 330 pf + c ext pf
output current output current derating as a function of the hybrid case temper- ature is provided in figure 10. the hybrid contains internal pulse by pulse current limit circuitry to limit the output current dur- ing fault conditions.(see table 2) current limit accuracy is +10/-15%. thermal operation it is recommended the pwr-82520 be mounted to a heat sink. this heat sink shall have the capacity to dissipate heat generat- ed by the hybrid at all levels of current output, up to the peak limit, while maintaining the case temperature limit as per fig- ure 10. 8 june 1, 2000; data device corp. current monitor out (pin 35) this is a bipolar analog output voltage representative of motor current. the current monitor output will have the same scaling as the current command input, 1.0 v/a. the output resistance will be less than 100 w . brush motor operation the pwr-82521 can also be used as a brush motor controller for current or voltage control in an h-bridge configuration. the pwr-82521 would be connected as shown in figure 8. all other connections are as shown in either figure 12 or 13 depending on current or voltage mode operation. the hall inputs are wired per table 4. a positive input command will result in positive current to the motor out of phase a. table 4. hall inputs for h-bridge controller h l l enable negative positive command in 1 1 1 ha 1 1 1 hb 0 0 0 hc input z l h ph a output z z z ph b z h l ph c phase a phase a phase c vbus- phase b vbus+ phase c hall c hall b hall a +15v hall supply out hall supply gnd 6 5 4 16 15 14 9 8 7 3 2 1 13 12 11 39 38 37 41 40 gnd +28v +5v +5v figure 8. brush motor hook up warning : the pwr-82521 does not have short circuit pro- tection. the pwr-82521 must see a minimum of 100uh induc- tive load or enought line-to-line resistance to limit the output current to <10a at all times. operation into a short or a condi- tion that requires excessive output current will damage the hybrid. table 3. commutation truth table inputs outputs enable dir ** ha hb hc phase a phase b phase c l cw 1 0 0 h l z l cw 1 1 0 h z l l cw 0 1 0 z h l l cw 0 1 1 l h z l cw 0 0 1 l z h l cw 1 0 1 z l h l ccw 1 0 1 z h l l ccw 0 0 1 h z l l ccw 0 1 1 h l z l ccw 0 1 0 z l h l ccw 1 1 0 l z h l ccw 1 0 0 l h z h z z z 1=logic voltage >3.5 vdc, 0=logic voltage < 0.7 vdc ** dir is based on the convention shown in figure 4. actual motor set up might be different.
9 june 1, 1999; data device corp. pwr-82521 power dissipation (see figure 11) there are two major contributors to power dissipation in the motor driver: conduction losses and switching losses. vbus = +28 v (bus voltage) io a = 3 a, i ob = 7 a (see figure 11) ton = 36 s, t = 40 s (period) (see figure 11) ron = 0.055 w (on-resistance, see table 2) rc = 0.133 w (conductor resistance, see table 2,) ts1 = 125 ns, ts2 = 200 ns (see figure 11) fo = 50 khz (switching frequency) 1. transistor conduction losses (pc) p t = (imotor rms) 2 x (ron) p t = (4.87) 2 x (0.055) p t = 1.30 watts continuous current (amps) case temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 140 28v, cont. cur. 42v, cont. cur. 70v, cont. cur. 11 10 9 8 7 6 5 4 3 2 1 0 2. switching losses (ps) ps = [ vcc ( i oa (ts1) + i ob (ts2) ) fo] / 2 ps = [ 28 v ( 3 a (125 ns) + 7 a (200 ns) ) 50 khz] / 2 ps = 1.24 watts transistor power dissipation ( p q ) p q = p t + ps p q = 1.30 + 1.24 = 2.54 watts output conductor dissipation p c = (imotor rms) 2 x (rc) p c = (4.87) 2 x (0.133) p c = 3.15 watts transistor power dissipation for continuous commutation p qc = p q (0.33) p qc = (2.54) x (0.33) p qc = 0.84 watts total hybrid power disipation p total = (p q + p c ) x 2 p total = (2.54 +3.15) x 2 p total = 11.38 watts i ob t on i oa vbus i o t s2 t s1 figure 11. output characteristics figure 10. motor current drive ( i ob i oa + (i ob - i oa ) 2 )( ton t ) 3 i motor rms = ( 7 * 3 + (7 - 3) 2 )( 36 ) 3 i motor rms = 40 accuracy = 5% (of rated output) -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -5 0 5 10 current (amps) input command (volt), inductive load figure 9. linearity curve
10 june 1, 2000; data device corp. figure 12. voltage control hook-up figure 13. torque control hook-up phase a phase a phase b phase c vbus- phase b vbus+ phase c rps c rps b rps a +15v rps supply out rps supply gnd c1 1000 f 100v r4 r3 r2 1k 1k 1k c3 2000pf c4 2000pf c5 2000pf 6 5 4 16 15 14 9 8 7 3 2 1 13 12 11 39 38 37 41 40 rps a rps b rps c rps supply gnd +15v rps supply output case gnd pwm in pwm out pwm gnd -15v supply supply gnd +15v supply command gnd command in - command in + error amp out command out error amp input current monitor out enable c6 47 f 35v c7 47 f 35v 17 19 20 21 26 27 28 29 30 31 32 33 34 35 36 10k 10k r2a 10k r2b 1meg r7 c1 4700pf r1 + + + gnd +28v motor bldc -15v gnd +15v command signal enable - - - optional cext cext + + + 470 pf phase a phase a phase b phase c vbus- phase b vbus+ phase c rps c rps b rps a +15v rps supply out rps supply gnd c1 1000 f 100v r4 r3 r2 1k 1k 1k c3 2000pf c4 2000pf c5 2000pf 6 5 4 16 15 14 9 8 7 3 2 1 13 12 11 39 38 37 41 40 rps a rps b rps c rps supply gnd +15v rps supply output case gnd pwm in pwm out pwm gnd -15v supply supply gnd +15v supply command gnd command in - command in + error amp out command out error amp input current monitor out enable c6 47 f 35v c7 47 f 35v 17 19 20 21 26 27 28 29 30 31 32 33 34 35 36 10k 10k r1 r5 + + + gnd +28v motor bldc -15v gnd +15v command signal enable - - - optional current monitor out cext + + + 470 pf
figure 14. mechanical outline 29.21 table 5. pin assignments pin function pin function 1 phase c 41 hall supply gnd 2 phase c 40 +15v hall supply output 3 phase c 39 ha 4 vbus + 38 hb 5 vbus + 37 hc 6 vbus + 36 enable 7 phase b 35 current monitor output 8 phase b 34 error amp input 9 phase b 33 command out 10 is+ 32 error amp out 11 vbus - 31 command in + 12 vbus - 30 command in - 13 vbus - 29 command gnd 14 phase a 28 +15v supply 15 phase a 27 supply gnd 16 phase a 26 -15v supply 25 n/c 24 n/c 23 n/c 22 sync 21 pwm gnd 20 pwm out 19 pwm in 18 n/c 17 case gnd note: 1. n/c pins have internal connections for factory test purposes. 11 june 1, 1999; data device corp.
12 june 1, 2000; data device corp. ordering information pwr-82521-xx0x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data *standard ddc processing with burn-in and full temperature test see table below. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7420 headquarters - tel: (631) 567-5600 ext. 7420, fax: (631) 567-7358 northern new jersey - tel: (908) 687-0441, fax: (908) 687-0470 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com standard ddc processing mil-std-883 test method(s) condition(s) inspection 2009, 2010, 2017, and 2032 seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 a burn-in 1015, table 1

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